The present invention relates to a chopping type comparator driven by an inverter for comparing a pair of input signals with each other.
FIG. 3 is a circuit diagram showing a structure of a conventional chopping type comparator. In the figure, there are provided a pair of input terminals A and B receptive, respectively, of input signal voltages VA and VB to be compared with each other. The comparator is further provided with a control terminal C receptive of a control signal CONT. A pair of analog switches 1 and 2 are comprised of a field effect transistor of the metal/oxide/semiconductor (MOS) structure. Respective one ends of the analog switches 1 and 2 are connected to the input terminals A and B, and respective other ends thereof are connected commonly to each other. The one analog switch 2 receives at its gate electrodes the control signal CONT, and the other analog switch 1 receives at its gate electrode an inverted one of the control signal CONT through an inverter 3. A capacitor 4 is connected at its one end to a common junction node of the analog switches 1 and 2. The other end of the capacitor 4 is connected to an input terminal of a complimentary MOS inverter or CMOS inverter 5. An analog switch 6 is connected between the input terminal and an output terminal OUT of the CMOS inverter 5, and is operated in response to the control signal CONT to switch between a conductive state and a nonconductive state.
In operation of the above described conventional comparator, the analog switches 2 and 6 are placed concurrently in the conductive state when the control signal CONT holds "1" level. Consequently, the input signal voltage VB is applied to the one end of the capacitor 4, and the CMOS inverter 5 is shorted between the input and output terminals thereof through the analog switch 6. In this operation, since the CMOS inverter 5 is composed of a pair of P channel transistor and N channel transistor having substantially the same driving ability, the CMOS inverter 5 has an input/output transfer characteristic terms of a varying input voltage VIN as shown in FIG. 4(a). As seen in the figure, as the input voltage VIN increases at the CMOS inverter 5, its output voltage VOUT is inverted from a high level to a low level when the input voltage VIN reaches a half level of a power supply voltage VDD. Therefore, the input voltage VIN and the output voltage VOUT are both held at VDD/2 because the CMOS inverter 5 is shorted between its input and output terminals through the conductive analog switch 6. Accordingly, when the control signal CONT is turned to "1" level, the capacitor 4 is charged to build up a voltage of VDD/2- VB at the one end thereof through the conductive analog switch 2.
Next, when the control signal CONT is turned to "0" level, the analog switches 2 and 6 are concurrently turned off while the analog switch 1 is placed in the conductive state so that the other signal voltage VA is applied to the one end of the capacitor 4. Consequently, the CMOS inverter 5 receives an input voltage VIN in the level of VDD/2-VB+VA which is a sum of the precedingly charged voltage VDD/2-VB and the succeedingly applied voltage VA. In cases of VA&gt;VB, VIN&gt;VDD/2 is held so that the output voltage VOUT of the CMOS inverter 5 is turned to a low level. On the other hand, in case of VA&lt;VB, VIN&lt;VDD/2 is held so that the output voltage VOUT of the CMOS inverter 5 is turned to a high level. By such operation, the CMOS inverter 5 produces the output voltage VOUT indicative of a comparison result between the pair of signal voltages VA and VB.
In the conventional chopping type comparator, as shown in FIG. 5, the input voltage VIN of the CMOS inverter 5 is held at the intermediate level of VDD/2 while the control signal CONT is turned to "1" level. As shown in FIG. 4(b), the CMOS inverter consumes a great amount of driving current I in case that the input voltage VIN is held around VDD/2. The considerable driving current I flows through the CMOS inverter 5 throughout a period during which the control signal CONT is held at "1" level as shown in FIGS. 5(a) and 5(c). Thus, the conventional chopping type comparator suffers from a wasteful power consumption.